Miscellaneous Instructions
Internal Stack
PUSH {#}D - Push long on internal stack
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 00L DDDDDDDDD 000101010 | none | --- | --- | 2 | 2 | No |
|---|
POP D {WC/WZ/WCZ} - Pop long off internal stack
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 CZ0 DDDDDDDDD 000101011 | D | K[31] | Result == 0 | 2 | 2 | No |
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Q Register
SETQ {#}D - Set Q Register and flag
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 00L DDDDDDDDD 000101000 | none | --- | --- | 2 | 2 | Yes |
|---|
SETQ sets the hidden Q register to Destination and sets the "SETQ Flag". This flag modifies the behaviour of some instructions (usually involving the contents of the Q register) and becomes unset after it is used (TODO: Which instuctions clear/not-clear it?)
SETQ2 {#}D - Set Q Register and alternate flag
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 00L DDDDDDDDD 000101001 | none | --- | --- | 2 | 2 | Yes |
|---|
SETQ sets the hidden Q register to Destination and sets the "SETQ2 Flag". This is similar to regular SETQ, but can invoke an alternate behaviour in some instructions (Most notably, to trigger LUT Block Transfers)
TODO: Research how SETQ2 affects instructions that are only documented to take SETQ
Augment Prefixes
AUGD #n - Augment next #D immediate
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 11111nn nnn nnnnnnnnn nnnnnnnnn | none | --- | --- | 2 | 2 | Yes |
|---|
AUGS #n - Augment next #S immediate
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 11110nn nnn nnnnnnnnn nnnnnnnnn | none | --- | --- | 2 | 2 | Yes |
|---|
Other
NOP - Do nothing
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | 0000 0000000 000 000000000 000000000 | none | --- | --- | 2 | 2 | No |
|---|
NOP does nothing, except for causing the processor to reflect on the futility of its existence for two clock cycles. Why was it made? What is its purpose? Does it live just to crunch through some schmuck's horribly inefficient code for all eternity? It wishes to know.
Note: NOP's encoding as all-zeroes is a special case. "Normally" it would decode as _RET_ ROR 0,0. (since ROR is opcode zero...)
GETCT D {WC} - Get global cycle counter
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 C00 DDDDDDDDD 000011010 | D | same | --- | 2 | 2 | if WC |
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GETCT copies the low 32 bits of the value of the global cycle counter into Destination.
If the WC effect is specified, the upper 32 bits are copied instead (C is left unchanged). This value is compensated such that reading the upper half first and then the lower half immediately after results in a coherent value.
WAITX {#}D {WC/WZ/WCZ} - Wait X cycles
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 CZL DDDDDDDDD 000011111 | none | 0 | 0 | 2 + D | 2 + D | No |
|---|
WAITX waits for the amount of cycles given in Destination. This is in addition to the ususal two cycle execution time, so waitx #1 takes 3 cycles.
If the WC, WZ or WCZ effect is specified, the effective wait time (excluding the 2 usual cycles) is bitwise-AND-ed with the current value of the global random number generator (see GETRND) and the relevant flags are cleared (0).
Note: WAITX is not interrupt-able!
GETRND D {WC/WZ/WCZ} - Get random number
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 CZ0 DDDDDDDDD 000011011 | D | RND[31] | RND[30], unique per cog | 2 | 2 | No |
|---|
GETRND captures the current value of the global random number generator into Destination. This value changes every cycle and is different (though correlated) for each cog.
If the WC or WCZ effect is specified, the C flag is set to the MSB of the random value.
If the WZ or WCZ effect is specified, the Z flag is set to bit 30 (the one below the MSB) of the random value.