Math and Logic Instructions

Data movement

MOV D,{#}S {WC/WZ/WCZ} - Move value

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0110000 CZI DDDDDDDDD SSSSSSSSS D S[31] Result == 0 2 2 No

MOV copies the Source value into Destination.

If the WC or WCZ effect is specified, the C flag is updated to be Source[31].

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination result equals zero, or is cleared (0) if it is non-zero.

MOVBYTS D,{#}S - Shuffle bytes in register

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001111 11I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

MOVBYTS shuffles the bytes of Destination based on bottom 8 bits in Source. Each bit pair in Source[7:0] corrosponds to one byte slot of the result and selects which of the input bytes will appear there. It is useful to use base-4 literals (%%0123) with MOVBYTS, since each digit corrosponds to one bit pair.

LOC PA/PB/PTRA/PTRB,#{\}A - Load address

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 11101WW RAA AAAAAAAAA AAAAAAAAA Per W --- --- 2 2 No

LOC moves a 20-bit address into either PA, PB, PTRA or PTRB. This address can be encoded as either absolute or relative.


GETNIB D,{#}S,#N - Get Nth nibble

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 100001N NNI DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

GETNIB reads the Nth nibble (4 bits) from Source and moves it into Destination. The upper 28 bits of Destination are cleared.

N can be any constant between 0 and 7. N = 0 gets the least significant nibble (S[3:0]), N = 7 gets the most significant nibble (S[31:28])

GETNIB can have its Source and N omitted, in which case they default to 0 and #0. This is intended for use with ALTGN.

GETBYTE D,{#}S,#N - Get Nth byte

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1000111 NNI DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

GETBYTE reads the Nth byte (8 bits) from Source and moves it into Destination. The upper 24 bits of Destination are cleared.

N can be any constant between 0 and 3. N = 0 gets the least significant byte (S[7:0]), N = 3 gets the most significant byte (S[31:24])

GETBYTE can have its Source and N omitted, in which case they default to 0 and #0. This is intended for use with ALTGB.

GETWORD D,{#}S,#N - Get Nth word

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001001 1NI DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

GETWORD reads the Nth word (16 bits) from Source and moves it into Destination. The upper 16 bits of Destination are cleared.

N can be the constants 0 and 1. N = 0 gets the least significant word (S[15:0]), N = 1 gets the most significant word (S[31:16])

GETWORD can have its Source and N omitted, in which case they default to 0 and #0. This is intended for use with ALTGW.


SETNIB D,{#}S,#N - Set Nth nibble

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 100000N NNI DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

SETNIB stores the least significant nibble (4 bits) of Source into the Nth nibble of Destination. All other bits are unaffected.

N can be any constant between 0 and 7. N = 0 sets the least significant nibble (D[3:0]), N = 7 sets the most significant nibble (D[31:28])

SETNIB can have its Destination and N omitted, in which case they default to 0 and #0. This is intended for use with ALTSN.

SETBYTE D,{#}S,#N - Set Nth byte

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1000110 NNI DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

SETBYTE stores the least significant byte (8 bits) of Source into the Nth byte of Destination. All other bits are unaffected.

N can be any constant between 0 and 3. N = 0 sets the least significant byte (D[7:0]), N = 3 sets the most significant byte (D[31:24])

SETBYTE can have its Destination and N omitted, in which case they default to 0 and #0. This is intended for use with ALTSB.

SETWORD D,{#}S,#N - Set Nth word

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001001 0NI DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

SETWORD stores the least significant byte (16 bits) of Source into the Nth word of Destination. All other bits are unaffected.

N can be the constants 0 and 1. N = 0 sets the least significant word (D[15:0]), N = 1 sets the most significant word (D[31:16])

SETWORD can have its Destination and N omitted, in which case they default to 0 and #0. This is intended for use with ALTSW.


ROLNIB D,{#}S,#N - Shift in Nth nibble

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 100010N NNI DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

ROLNIB reads the Nth nibble (4 bits) from Source and shifts it into Destination. The lower 28 bits of Destination are shifted up by 4 and the top 4 bits are discarded.

N can be any constant between 0 and 7. N = 0 gets the least significant nibble (S[3:0]), N = 7 gets the most significant nibble (S[31:28])

ROLNIB can have its Source and N omitted, in which case they default to 0 and #0. This is intended for use with ALTGN.

ROLBYTE D,{#}S,#N - Shift in Nth byte

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001000 NNI DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

ROLBYTE reads the Nth byte (8 bits) from Source and shifts it into Destination. The lower 24 bits of Destination are shifted up by 8 and the top 8 bits are discarded.

N can be any constant between 0 and 3. N = 0 gets the least significant byte (S[7:0]), N = 3 gets the most significant byte (S[31:24])

ROLBYTE can have its Source and N omitted, in which case they default to 0 and #0. This is intended for use with ALTGB.

ROLWORD D,{#}S,#N - Shift in Nth word

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001010 0NI DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

ROLWORD reads the Nth word (16 bits) from Source and shifts it into Destination. The lower 16 bits of Destination are shifted up by 16 and the top 16 bits are discarded.

N can be the constants 0 and 1. N = 0 gets the least significant word (S[15:0]), N = 1 gets the most significant word (S[31:16])

ROLWORD can have its Source and N omitted, in which case they default to 0 and #0. This is intended for use with ALTGW.


SETS D,{#}S - Set S field

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001101 11I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

SETS copies Source[8:0] into Destination[8:0]. Other bits remain unaffected. This is useful to set up the S-field for ALTI or to set the S-field of an instruction in memory (See: Self-Modifying Code TODO Link).

SETD D,{#}S - Set D field

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001101 10I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

SETD copies Source[8:0] into Destination[17:9]. Other bits remain unaffected. This is useful to set up the D field for ALTI or to set the D field of an instruction in memory (See: Self-Modifying Code TODO Link).

SETR D,{#}S - Set R field

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001101 01I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

SETR copies Source[8:0] into Destination[27:19]. Other bits remain unaffected. This is useful to set up the R field for ALTI or to modify the opcode and flag effects of an instruction in memory (See: Self-Modifying Code TODO Link).

Arithmetic

ADD D,{#}S {WC/WZ/WCZ} - Unsigned add

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0001000 CZI DDDDDDDDD SSSSSSSSS D carry of (D + S) Result == 0 2 2 No

ADD sums the two unsigned values of Destination and Source together and stores the result into the Destination register.

If the WC or WCZ effect is specified, the C flag is set (1) if the summation resulted in an unsigned carry (= 32-bit overflow), or is cleared (0) if no carry.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result stored into Destination is zero, or is cleared (0) if it is non-zero.

To add unsigned, multi-long values, use ADD followed by ADDX as described in Adding Two Multi-Long Values(TODO LINK). ADD and ADDX are also used in adding signed, multi-long values with ADDSX ending the sequence.

ADDS D,{#}S {WC/WZ/WCZ} - Signed add

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0001010 CZI DDDDDDDDD SSSSSSSSS D correct sign of (D + S) Result == 0 2 2 No

ADDS sums the two signed values of Destination and Source together and stores the result into the Destination register. If Source is a 9-bit literal, its value is interpreted as positive (0-511; it is not sign-extended) — use ##Value (or insert a prior AUGS instruction) for a 32-bit signed value; negative or positive.

If the WC or WCZ effect is specified, the C flag is set (1) if the summation, signed overflow nonwithstanding, produced a negative result. Overflow occured if C is not equal to the result's MSB (see TJV).

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result stored into Destination is zero, or is cleared (0) if it is non-zero.

To add signed, multi-long values, use ADD (not ADDS) followed possibly by ADDX, and finally ADDSX as described in Adding Two Multi-Long Values(TODO LINK).

ADDX D,{#}S {WC/WZ/WCZ} - Unsigned add with carry

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0001001 CZI DDDDDDDDD SSSSSSSSS D carry of (D + S + C) Z AND (result == 0) 2 2 No

ADDX sums the unsigned values of Destination and Source plus C together and stores the result into the Destination register. The ADDX instruction is used to perform unsigned multi-long (extended) addition, such as 64-bit addition.

If the WC or WCZ effect is specified, the C flag is set (1) if the summation resulted in an unsigned carry, or is cleared (0) if no carry.

If the WZ or WCZ effect is specified, the Z flag is set (1) if Z was previously set and the result stored into Destination is zero, or it is cleared (0) if non-zero or if Z was not previously set. Use WCZ on preceding ADD and ADDX instructions for proper final Z flag.

To add unsigned multi-long values, use ADD followed by one or more ADDX instructions as described in Adding Two Multi-Long Values(TODO LINK).

ADDSX D,{#}S {WC/WZ/WCZ} - Signed add with carry

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0001011 CZI DDDDDDDDD SSSSSSSSS D correct sign of (D + S + C) Z AND (result == 0) 2 2 No

ADDSX sums the signed values of Destination and Source plus C together and stores the result into the Destination register. The ADDSX instruction is used to perform signed multi-long (extended) addition, such as 64-bit addition.

If the WC or WCZ effect is specified, the C flag is set (1) if the summation, signed overflow nonwithstanding, produced a negative result. Overflow occured if C is not equal to the result's MSB (see TJV).

If the WZ or WCZ effect is specified, the Z flag is set (1) if Z was previously set and the result stored into Destination is zero, or it is cleared (0) if non-zero or if Z was not previously set. Use WCZ on preceding ADD and ADDX instructions for proper final Z flag.

To add signed multi-long values, use ADD (not ADDS) followed possibly by ADDX, and finally ADDSX as described in Adding Two Multi-Long Values(TODO LINK).


SUB D,{#}S {WC/WZ/WCZ} - Unsigned subtract

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0001100 CZI DDDDDDDDD SSSSSSSSS D borrow of (D - S) Result == 0 2 2 No

SUB subtracts the unsigned Source from the unsigned Destination and stores the result into the Destination register.

If the WC or WCZ effect is specified, the C flag is set (1) if the subtraction results in an unsigned borrow (= 32-bit underflow), or is cleared (0) if no borrow.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result stored into Destination is zero, or is cleared (0) if it is non-zero.

To subtract unsigned, multi-long values, use SUB followed by SUBX as described in Subtracting Two Multi-Long Values(TODO LINK). SUB and SUBX are also used in subtracting signed, multi-long values with SUBSX ending the sequence.

SUBR D,{#}S {WC/WZ/WCZ} - Reverse subtract

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0010110 CZI DDDDDDDDD SSSSSSSSS D borrow of (S - D) Result == 0 2 2 No

SUBR subtracts the unsigned Destination from the unsigned Source and stores the result into the Destination register. This is the reverse of the subtraction order of SUB.

If the WC or WCZ effect is specified, the C flag is set (1) if the subtraction results in an unsigned borrow (= 32-bit underflow), or is cleared (0) if no borrow.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result stored into Destination is zero, or is cleared (0) if it is non-zero.

SUBS D,{#}S {WC/WZ/WCZ} - Signed subtract

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0001110 CZI DDDDDDDDD SSSSSSSSS D correct sign of (D - S) Result == 0 2 2 No

SUBS subtracts the signed Source from the signed Destination and stores the result into the Destination register. If Source is a 9-bit literal, its value is interpreted as positive (0-511; it is not sign-extended) — use ##Value (or insert a prior AUGS instruction) for a 32-bit signed value; negative or positive.

If the WC or WCZ effect is specified, the C flag is set (1) if the subtraction, signed overflow nonwithstanding, produced a negative result. Overflow occured if C is not equal to the result's MSB (see TJV).

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result stored into Destination is zero, or is cleared (0) if it is non-zero.

To subtract signed, multi-long values, use SUB (not SUBS) followed possibly by SUBX, and finally SUBSX as described in Subtracting Two Multi-Long Values(TODO LINK).

SUBX D,{#}S {WC/WZ/WCZ} - Unsigned subtract with borrow

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0001101 CZI DDDDDDDDD SSSSSSSSS D borrow of (D - (S + C)) Z AND (result == 0) 2 2 No

SUBX subtracts the unsigned value of Source plus C from the unsigned Destination and stores the result into the Destination register. The SUBX instruction is used to perform unsigned multi-long (extended) subtraction, such as 64-bit subtraction.

If the WC or WCZ effect is specified, the C flag is set (1) if the subtraction resulted in an unsigned borrow, or is cleared (0) if no carry.

If the WZ or WCZ effect is specified, the Z flag is set (1) if Z was previously set and the result stored into Destination is zero, or it is cleared (0) if non-zero or if Z was not previously set. Use WCZ on preceding SUB and SUBX instructions for proper final Z flag.

SUBSX D,{#}S {WC/WZ/WCZ} - Signed subtract with borrow

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0001111 CZI DDDDDDDDD SSSSSSSSS D correct sign of (D - (S + C)) Z AND (result == 0) 2 2 No

SUBSX subtracts the signed value of Source plus C from the signed Destination and stores the result into the Destination register. The SUBSX instruction is used to perform signed multi-long (extended) subtraction, such as 64-bit subtraction.

If the WC or WCZ effect is specified, the C flag is set (1) if the subtraction, signed overflow nonwithstanding, produced a negative result. Overflow occured if C is not equal to the result's MSB (see TJV).

If the WZ or WCZ effect is specified, the Z flag is set (1) if Z was previously set and the result stored into Destination is zero, or it is cleared (0) if non-zero or if Z was not previously set. Use WCZ on preceding SUB and SUBX instructions for proper final Z flag.

To subtract signed multi-long values, use SUB (not SUBS) followed possibly by SUBX, and finally SUBSX as described in Subtracting Two Multi-Long Values(TODO LINK).


CMP D,{#}S {WC/WZ/WCZ} - Unsigned compare

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0010000 CZI DDDDDDDDD SSSSSSSSS none borrow of (D - S) (D == S) 2 2 No

CMP compares the unsigned values of Destination and Source (by subtracting Source from Destination) and optionally setting the C and Z flags accordingly.

If the WC or WCZ effect is specified, the C flag is set (1) if Destination is less than Source.

If the WZ or WCZ effect is specified, the Z flag is set (1) if Destination equals Source.

Note that it is possible to encode CMP without any effects, which is entirely pointless.

CMPR D,{#}S {WC/WZ/WCZ} - Reverse compare

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0010100 CZI DDDDDDDDD SSSSSSSSS none borrow of (S - D) (D == S) 2 2 No

CMPR compares the unsigned values of Destination and Source (by subtracting Destination from Source) and optionally setting the C and Z flags accordingly.

If the WC or WCZ effect is specified, the C flag is set (1) if Source is less than Destination.

If the WZ or WCZ effect is specified, the Z flag is set (1) if Destination equals Source.

Note that it is possible to encode CMP without any effects, which is entirely pointless.

CMPS D,{#}S {WC/WZ/WCZ} - Signed compare

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0010010 CZI DDDDDDDDD SSSSSSSSS none correct sign of (D - S) (D == S) 2 2 No

CMPS compares the signed values of Destination and Source (by subtracting Source from Destination) and optionally setting the C and Z flags accordingly.

If the WC or WCZ effect is specified, the C flag is set (1) if Destination is less than Source.

If the WZ or WCZ effect is specified, the Z flag is set (1) if Destination equals Source.

Note that it is possible to encode CMPS without any effects, which is entirely pointless.

CMPM D,{#}S {WC/WZ/WCZ} - MSB compare

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0010101 CZI DDDDDDDDD SSSSSSSSS none MSB of (D - S) (D == S) 2 2 No

CMPM compares the values of Destination and Source (by subtracting Source from Destination) and optionally setting the C and Z flags accordingly.

If the WC or WCZ effect is specified, the C flag is updated to the MSB (bit 31) of (Destination - Source)

If the WZ or WCZ effect is specified, the Z flag is set (1) if Destination equals Source.

Note that it is possible to encode CMPM without any effects, which is entirely pointless.

CMPSUB D,{#}S {WC/WZ/WCZ} - Compare and subtract

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0010111 CZI DDDDDDDDD SSSSSSSSS D D >= S Result == 0 2 2 No

CMPSUB compares the unsigned values of Destination and Source, and, if Source is less than or equal to Destination, it is subtracted from Destination. Optionally, the C and Z flags are set to indicate the comparison and operation results.

If the WC or WCZ effect is specified, the C flag is set (1) if Destination was greater than or equal to Source.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result equals 0 (including if Destination was 0 to begin with).

CMPX D,{#}S {WC/WZ/WCZ} - Unsigned compare with borrow

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0010001 CZI DDDDDDDDD SSSSSSSSS none borrow of (D - (S + C)) Z AND (D == S + C) 2 2 No

CMPSX D,{#}S {WC/WZ/WCZ} - Signed compare with borrow

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0010011 CZI DDDDDDDDD SSSSSSSSS none correct sign of (D - (S + C)) Z AND (D == S + C) 2 2 No

ABS D,{#}S {WC/WZ/WCZ} - Absolute value

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0110010 CZI DDDDDDDDD SSSSSSSSS D S[31] Result == 0 2 2 No

ABS determines the absolute value of Source and writes the result into Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the original Source value was negative, or is cleared (0) if it was positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

Literal Source values are zero-extended, so ABS is really best used with register Source (or augmented Source) values.

ABS's Source can be omitted, in which case it defaults to being the same as its Destination.

NEG D,{#}S {WC/WZ/WCZ} - Negate value

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0110011 CZI DDDDDDDDD SSSSSSSSS D MSB of result Result == 0 2 2 No

NEG negates Source and stores the result in the Destination register. The negation flips the value's sign; ex: 78 becomes -78, or -306 becomes 306.

If the WC or WCZ effect is specified, the C flag is set (1) if the result is negative, or is cleared (0) if positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

NEG's Source can be omitted, in which case it defaults to being the same as its Destination.

NEGC D,{#}S {WC/WZ/WCZ} - Negate if C

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0110100 CZI DDDDDDDDD SSSSSSSSS D MSB of result Result == 0 2 2 No

NEGC negates Source if the C flag is set and stores the result in the Destination register. If the C flag is clear, the Source value is left as-is (not negated) and is stored into Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result is negative, or is cleared (0) if positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

NEGNC D,{#}S {WC/WZ/WCZ} - Negate if !C

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0110101 CZI DDDDDDDDD SSSSSSSSS D MSB of result Result == 0 2 2 No

NEGNC negates Source if the C flag is not set and stores the result in the Destination register. If the C flag is set, the Source value is left as-is (not negated) and is stored into Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result is negative, or is cleared (0) if positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

NEGZ D,{#}S {WC/WZ/WCZ} - Negate if Z

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0110110 CZI DDDDDDDDD SSSSSSSSS D MSB of result Result == 0 2 2 No

NEGZ negates Source if the C flag is set and stores the result in the Destination register. If the Z flag is clear, the Source value is left as-is (not negated) and is stored into Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result is negative, or is cleared (0) if positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

NEGNZ D,{#}S {WC/WZ/WCZ} - Negate if !Z

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0110111 CZI DDDDDDDDD SSSSSSSSS D MSB of result Result == 0 2 2 No

NEGNZ negates Source if the Z flag is not set and stores the result in the Destination register. If the Z flag is set, the Source value is left as-is (not negated) and is stored into Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result is negative, or is cleared (0) if positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.


SUMC D,{#}S {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0011100 CZI DDDDDDDDD SSSSSSSSS D correct sign of (D +/- S) Result == 0 2 2 No

SUMC subtracts Source from Destination if the C flag is set and stores the result in the Destination register. If the C flag is clear, Source is instead added to Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result is negative, or is cleared (0) if positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

SUMNC D,{#}S {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0011101 CZI DDDDDDDDD SSSSSSSSS D correct sign of (D +/- S) Result == 0 2 2 No

SUMNC subtracts Source from Destination if the C flag is not set and stores the result in the Destination register. If the C flag is set, Source is instead added to Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result is negative, or is cleared (0) if positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

SUMZ D,{#}S {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0011110 CZI DDDDDDDDD SSSSSSSSS D correct sign of (D +/- S) Result == 0 2 2 No

SUMZ subtracts Source from Destination if the Z flag is set and stores the result in the Destination register. If the Z flag is clear, Source is instead added to Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result is negative, or is cleared (0) if positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

SUMNZ D,{#}S {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0011111 CZI DDDDDDDDD SSSSSSSSS D correct sign of (D +/- S) Result == 0 2 2 No

SUMNZ subtracts Source from Destination if the Z flag is not set and stores the result in the Destination register. If the Z flag is set, Source is instead added to Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result is negative, or is cleared (0) if positive.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.


MUL D,{#}S {WZ} - Unsigned 16-bit multiply

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1010000 0ZI DDDDDDDDD SSSSSSSSS D --- (S == 0) | (D == 0) 2 2 No

MUL performs an unsigned multiplication of the lower 16-bits of Destination and Source and stores the 32-bit product result into the Destination register. This is a fast (2-clock) 16 x 16 bit multiplication operation - to multiply larger factors, use the CORDIC Solver QMUL instruction.

If the WZ effect is specified, the Z flag is set (1) if either the Destination or Source values are zero, or is cleared (0) if both are non-zero. TODO: is the entire register checked or just the bottom 16 bits?

MULS D,{#}S {WZ} - Signed 16-bit multiply

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1010000 1ZI DDDDDDDDD SSSSSSSSS D --- (S == 0) | (D == 0) 2 2 No

MULS performs a signed multiplication of the lower 16-bits of Destination and Source and stores the 32-bit signed product result into the Destination register. This is a fast (2-clock) signed 16 x 16 bit multiplication operation - to multiply larger factors, use the CORDIC Solver QMUL instruction.

If the WZ effect is specified, the Z flag is set (1) if either the Destination or Source values are zero, or is cleared (0) if both are non-zero. TODO: same question as MUL

SCA D,{#}S {WZ} - Unsigned 16-bit scale

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1010001 0ZI DDDDDDDDD SSSSSSSSS none --- Result == 0 2 2 Yes

SCA performs an unsigned multiplication of the lower 16-bits of Destination and Source, shifts the 32-bit product right by 16 (to scale down the result), and substitutes this value as the next instruction's Source value.

If the WZ effect is specified, the Z flag is set (1) if the product (before scaling down) is zero, or is cleared (0) if non-zero.

SCAS D,{#}S {WZ} - Signed 16-bit scale

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1010001 1ZI DDDDDDDDD SSSSSSSSS none --- Result == 0 2 2 Yes

SCAS performs a signed multiplication of the lower 16-bits of Destination and Source, right shifts the 32-bit product by 14 (to scale down the result), and substitutes this value as the next instruction's Source value.

In this 2.14 fixed point scheme, a factor of $4000 will pass the the other factor through unchanged and a factor of $C000 will negate it.

If the WZ effect is specified, the Z flag is set (1) if the product (before scaling down) is zero, or is cleared (0) if non-zero.


INCMOD D,{#}S {WC/WZ/WCZ} - Increment with modulus

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0111000 CZI DDDDDDDDD SSSSSSSSS D D == S Result == 0 2 2 No

INCMOD compares Destination with Source - if not equal, it increments Destination; otherwise it sets Destination to 0. If Destination begins in the range 0 to Source, iterations of INCMOD will increment Destination repetitively from 0 to Source.

If the WC or WCZ effect is specified, the C flag is set (1) if Destination was equal to Source and subsequently reset to 0; or is cleared (0) if not reset.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

INCMOD does not limit Destination within the specified range - if Destination begins as greater than Source, iterations of INCMOD will continue to increment it through the 32-bit rollover point (back to 0) before it will effectively cycle from 0 to Source.

DECMOD D,{#}S {WC/WZ/WCZ} - Decrement with modulus

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0111001 CZI DDDDDDDDD SSSSSSSSS D D == 0 Result == 0 2 2 No

DECMOD compares Destination with 0 - if not equal, it decrements Destination; otherwise it sets Destination to Source. If Destination begins in the range 0 to Source, iterations of DECMOD will decrement Destination repetitively from Source to 0.

If the WC or WCZ effect is specified, the C flag is set (1) if Destination was equal to 0 and subsequently reset to Source; or is cleared (0) if not reset.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

DECMOD does not limit Destination within the specified range - if Destination begins as greater than Source, iterations of DECMOD will continue to decrement it down through Source before it will effectively cycle from Source to 0.


FGE D,{#}S {WC/WZ/WCZ} - Limit minimum (unsigned)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0011000 CZI DDDDDDDDD SSSSSSSSS D D < S Result == 0 2 2 No

FGE sets Destination to Source if Destination is less than Source by unsigned comparsion. This is also known as a limit minimum function; preventing Destination from sinking below Source.

If the WC or WCZ effect is specified, the C flag is set (1) if Destination was limited (Destination was less than Source and now Destination is equal to Source), or is cleared (0) if not limited.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

FGES D,{#}S {WC/WZ/WCZ} - Limit minimum (signed)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0011010 CZI DDDDDDDDD SSSSSSSSS D D < S Result == 0 2 2 No

FGES sets Destination to Source if Destination is less than Source by signed comparsion. This is also known as a limit minimum function; preventing Destination from sinking below Source.

If the WC or WCZ effect is specified, the C flag is set (1) if Destination was limited (Destination was less than Source and now Destination is equal to Source), or is cleared (0) if not limited.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

FLE D,{#}S {WC/WZ/WCZ} - Limit maximum (unsigned)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0011001 CZI DDDDDDDDD SSSSSSSSS D D > S Result == 0 2 2 No

FLE sets Destination to Source if Destination is greater than Source by unsigned comparsion. This is also known as a limit maximum function; preventing Destination from rising above Source.

If the WC or WCZ effect is specified, the C flag is set (1) if Destination was limited (Destination was greater than Source and now Destination is equal to Source), or is cleared (0) if not limited.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

FLES D,{#}S {WC/WZ/WCZ} - Limit maximum (signed)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0011011 CZI DDDDDDDDD SSSSSSSSS D D > S Result == 0 2 2 No

FLES sets Destination to Source if Destination is greater than Source by signed comparsion. This is also known as a limit maximum function; preventing Destination from rising above Source.

If the WC or WCZ effect is specified, the C flag is set (1) if Destination was limited (Destination was greater than Source and now Destination is equal to Source), or is cleared (0) if not limited.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

Bit operations

SHL D,{#}S {WC/WZ/WCZ} - Shift bits left

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0000011 CZI DDDDDDDDD SSSSSSSSS D last bit shifted out if S[4:0] > 0, else D[31] Result == 0 2 2 No

SHL shifts Destination's binary value left by Source places (0–31 bits) and sets the new LSBs to 0. This is useful for bit-stream manipulation as well as for swift multiplication; signed or unsigned 32-bit integer multiplication by a power-of-two. Care must be taken for power-of-two multiplications since upper bits will shift through the MSB (sign bit); mangling large signed values.

If the WC or WCZ effect is specified, the C flag is updated to the value of the last bit shifted out (effectively C = result bit "32") if Source is 1–31, or to Destination[31] if Source is 0.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination result equals zero, or is cleared (0) if it is non-zero.

SHR D,{#}S {WC/WZ/WCZ} - Shift bits right

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0000010 CZI DDDDDDDDD SSSSSSSSS D last bit shifted out if S[4:0] > 0, else D[0] Result == 0 2 2 No

SHR shifts Destination's binary value right by Source places (0–31 bits) and sets the new MSBs to 0. This is useful for bit-stream manipulation as well as for swift division; unsigned 32-bit integer division by a power-of-two. For similar division of a signed value, use SAR instead.

If the WC or WCZ effect is specified, the C flag is updated to the value of the last bit shifted out (effectively C = result bit "-1") if Source is 1–31, or to Destination[0] if Source is 0.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination result equals zero, or is cleared (0) if it is non-zero.

SAL D,{#}S {WC/WZ/WCZ} - Rarely useful

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0000111 CZI DDDDDDDDD SSSSSSSSS D last bit shifted out if S[4:0] > 0, else D[31] Result == 0 2 2 No

SAL shifts Destination's binary value left by Source places (0–31 bits) and sets the new LSBs to that of the original Destination[0]. SAL is the complement of SAR for bit streams but not for math operations - use SHL instead for swift 32-bit integer multiplication by a power-of-two.

If the WC or WCZ effect is specified, the C flag is updated to the value of the last bit shifted out (effectively C = result bit "32") if Source is 1–31, or to Destination[31] if Source is 0.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination result equals zero, or is cleared (0) if it is non-zero.

SAR D,{#}S {WC/WZ/WCZ} - Shift arithmetic right

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0000110 CZI DDDDDDDDD SSSSSSSSS D last bit shifted out if S[4:0] > 0, else D[0] Result == 0 2 2 No

SAR shifts Destination's binary value right by Source places (0–31 bits) and sets the new MSBs to that of the original Destination[31]; preserving the sign of a signed integer. This is useful for bit stream manipulation and for swift division - it is similar to SHR for swift division by a power-of-two, but is safe for both signed and unsigned integers. (Note that the rounding behaviour for negative numbers is different to a real division - TODO: Describe this better)

If the WC or WCZ effect is specified, the C flag is updated to the value of the last bit shifted out (effectively C = result bit "-1") if Source is 1–31, or to Destination[0] if Source is 0.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination result equals zero, or is cleared (0) if it is non-zero.

ROL D,{#}S {WC/WZ/WCZ} - Rotate bits left

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0000001 CZI DDDDDDDDD SSSSSSSSS D last bit shifted out if S[4:0] > 0, else D[31] Result == 0 2 2 No

ROL rotates Destination's binary value left by Source places (0–31 bits). All MSBs rotated out are moved into the new LSBs.

If the WC or WCZ effect is specified, the C flag is updated to the value of the last bit rotated out (effectively C = result bit "0") if Source is 1–31, or to Destination[31] if Source is 0.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination result equals zero, or is cleared (0) if it is non-zero. Since no bits are lost by this operation, the result will only be zero if Destination started at zero.

ROR D,{#}S {WC/WZ/WCZ} - Rotate bits right

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0000000 CZI DDDDDDDDD SSSSSSSSS D last bit shifted out if S[4:0] > 0, else D[0] Result == 0 2 2 No

ROR rotates Destination's binary value right by Source places (0–31 bits). All LSBs rotated out are moved into the new MSBs.

If the WC or WCZ effect is specified, the C flag is updated to the value of the last bit rotated out (effectively C = result bit "31") if Source is 1–31, or to Destination[0] if Source is 0.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination result equals zero, or is cleared (0) if it is non-zero. Since no bits are lost by this operation, the result will only be zero if Destination started at zero.

RCL D,{#}S {WC/WZ/WCZ} - Rotate carry left

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0000101 CZI DDDDDDDDD SSSSSSSSS D last bit shifted out if S[4:0] > 0, else D[31] Result == 0 2 2 No

RCL shifts Destination's binary value left by Source places (0–31 bits) and sets the new LSBs to C.

If the WC or WCZ effect is specified, the C flag is updated to the value of the last bit shifted out if Source is 1–31, or to Destination[31] if Source is 0.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination result equals zero, or is cleared (0) if it is non-zero.

RCR D,{#}S {WC/WZ/WCZ} - Rotate carry right

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0000100 CZI DDDDDDDDD SSSSSSSSS D last bit shifted out if S[4:0] > 0, else D[0] Result == 0 2 2 No

RCR shifts Destination's binary value right by Source places (0–31 bits) and sets the new MSBs to C.

If the WC or WCZ effect is specified, the C flag is updated to the value of the last bit shifted out if Source is 1–31, or to Destination[0] if Source is 0.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination result equals zero, or is cleared (0) if it is non-zero.

RCZL D {WC/WZ/WCZ} - Rotate flags left

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 DDDDDDDDD 001101011 D D[31] D[30] 2 2 No

RCZL shifts Destination's binary value left by two places and sets Destination[1] to C and Destination[0] to Z.

If the WC or WCZ effect is specified, the C flag is updated to the original Destination[31] state.

If the WZ or WCZ effect is specified, the Z is flag is updated to the original Destination[30] state.

RCZR D {WC/WZ/WCZ} - Rotate flags right

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 DDDDDDDDD 001101010 D D[1] D[0] 2 2 No

RCZR shifts Destination's binary value right by two places and sets Destination[31] to C and Destination[30] to Z.

If the WC or WCZ effect is specified, the C flag is updated to the original Destination[1] state.

If the WZ or WCZ effect is specified, the Z is flag is updated to the original Destination[0] state.

SIGNX D,{#}S {WC/WZ/WCZ} - Sign-extend

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0111011 CZI DDDDDDDDD SSSSSSSSS D MSB of result Result == 0 2 2 No

SIGNX fills the bits of Destination, above the bit indicated by Source[4:0], with the value of that identified bit; i.e. sign-extending the value. This is handy when converting encoded or received signed values from a small bit width to a large bit with; i.e. 32 bits.

Note: To extend an N-bit value, Source[4:0] has to be N-1. (TODO: Clarify this in a less confusing way)

If the WC or WCZ effect is specified, the C flag is set to the result's MSB value.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.

ZEROX D,{#}S {WC/WZ/WCZ} - Zero-extend

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0111010 CZI DDDDDDDDD SSSSSSSSS D MSB of result Result == 0 2 2 No

ZEROX fills the bits of Destination, above the bit indicated by Source[4:0], with zeroes; i.e. zero-extending the value. This is handy when converting encoded or received unsigned values from a small bit width to a large bit with; i.e. 32 bits.

Note: To extend an N-bit value, Source[4:0] has to be N-1. (TODO: Clarify this in a less confusing way)

If the WC or WCZ effect is specified, the C flag is set to the result's MSB value. This is always zero unless Source[4:0] == 31.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result is zero, or is cleared (0) if it is non-zero.


NOT D,{#}S {WC/WZ/WCZ} - Bitwise NOT

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0110001 CZI DDDDDDDDD SSSSSSSSS D !S[31] Result == 0 2 2 No

NOT performs a bitwise NOT (inverting all bits) of the value in Source and stores the result into Destination.

If the WC or WCZ effect is specified, the C flag value is replaced by the inverse of either S[31].

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result (of !Source) equals zero, or is cleared (0) if it is non-zero.

ONES D,{#}S {WC/WZ/WCZ} - Population count

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0111101 CZI DDDDDDDDD SSSSSSSSS D LSB of result Result == 0 2 2 No

ONES tallies the number of high bits of Source, or Destination, and stores the count into Destination. This is also known as a "Population Count" ("popcount") function.

If the WC or WCZ effect is specified, the C flag is set (1) if the count is odd, or is cleared (0) if it is even.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result equals zero, or is cleared (0) if not zero.

ONES' Source can be omitted, in which case it defaults to being the same as its Destination.

ENCOD D,{#}S {WC/WZ/WCZ} - Find highest set bit

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0111100 CZI DDDDDDDDD SSSSSSSSS D (S != 0) Result == 0 2 2 No

ENCOD stores the bit position value (0—31) of the top-most high bit (1) of Source into Destination. If the value to encode is all zeroes, the resulting Destination will be 0 - use the WC or WCZ effect and check the resulting C flag to distinguish between the cases of Source == 1 vs. Source == 0.

If the WC or WCZ effect is specified, the C flag is set (1) if Source was not zero, or is cleared (0) if it was zero.

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result equals zero, or is cleared (0) if not zero.

ENCOD is the complement of DECOD.

ENCOD's Source can be omitted, in which case it defaults to being the same as its Destination.

DECOD D,{#}S - Get Nth power of 2

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001110 00I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

DECOD generates a 32-bit value with just one bit high, corresponding to Source[4:0] (0—31) and stores that result in Destination.

In effect, Destination becomes 1 << value via the DECOD instruction; where value is Source[4:0].

DECOD is the complement of ENCOD

DECOD's Source can be omitted, in which case it defaults to being the same as its Destination.

BMASK D,{#}S - Get mask of lower N bits

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001110 01I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

BMASK generates an LSB-justified bit mask (all ones) of Source[4:0]+1 bits and stores it in Destination. The size value, specified by Source[4:0], is in the range 0—31 to generate 1 to 32 bits of bit mask.

In effect, Destination becomes (%10 << size) - 1 via the BMASK instruction.

A bit mask is often useful in bitwise operations (AND, OR, XOR) to filter out or affect special groups of bits.

BMASK's Source can be omitted, in which case it defaults to being the same as its Destination.


REV D - Reverse bits

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001101001 D --- --- 2 2 No

REV performs a bitwise reverse (bits 31:0 -> bits 0:31) of the value in Destination and stores the result back into Destination. This is useful for processing binary data in a different MSB/LSB order than it is transmitted with.

SPLITB D - Split nibble bits into bytes

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001100000 D --- --- 2 2 No

MERGEB D - Merge bytes into nibbles

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001100001 D --- --- 2 2 No

SPLITB and MERGEB reorder the bits within Destination in a complementary pattern. 0 0 1 8 2 16 3 24 4 1 5 9 6 17 7 25 8 2 9 10 10 18 11 26 12 3 13 11 14 19 15 27 16 4 17 12 18 20 19 28 20 5 21 13 22 21 23 29 24 6 25 14 26 22 27 30 28 7 29 15 30 23 31 31 SPLITB Splits groups of four bits in D into four bytes. MERGEB Merges four bytes in D into groups of four bits. TODO more text

SPLITW D - Split odd/even bits into high/low words

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001100010 D --- --- 2 2 No

MERGEW D - Merge high/low words into odd/even bits

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001100011 D --- --- 2 2 No

SPLITW and MERGEW reorder the bits within Destination in a complementary pattern. 0 0 1 16 2 1 3 17 4 2 5 18 6 3 7 19 8 4 9 20 10 5 11 21 12 6 13 22 14 7 15 23 16 8 17 24 18 9 19 25 20 10 21 26 22 11 23 27 24 12 25 28 26 13 27 29 28 14 29 30 30 15 31 31 SPLITW Splits odd/even bits in D into high/low words. MERGEW Merges high/low words in D into odd/even bits. TODO more text

RGBEXP D - Convert RGB565 to RGBx8888

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001100111 D --- --- 2 2 No

RGBSQZ D - Convert RGBx8888 to RGB565

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001100110 D --- --- 2 2 No

RGBEXP and RGBSQZ convert between RGBx8888 and RGB565 color values.

0 11 1 12 2 13 8 3 14 9 4 15 10 5 18 6 19 7 20 8 21 9 22 16 10 23 17 11 27 12 28 13 29 24 14 30 25 15 31 26 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RGBEXP Expands RGB Color. RGBSQZ Squeezes RGB Color.

TODO RGBEXP text

RGBSQZ converts a 32-bit color in Destination into a 16-bit color. This can be described as moving Destination[15:11] to Destination[4:0], Destination[23:18] into Destination[10:5], Destination[31:27] into Destination[15:11] and clearing the remaining 16 bits.

SEUSSF D - Scramble bits (forward)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001100100 D --- --- 2 2 No

SEUSSR D - Scramble bits (reverse)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001100101 D --- --- 2 2 No

SEUSSF and SEUSSR are TODO weird. What are these actually good for? 0 11 1 5 2 18 3 24 4 27 5 19 6 20 7 30 8 28 9 26 10 21 11 25 12 3 13 8 14 7 15 23 16 13 17 12 18 16 19 2 20 15 21 1 22 9 23 31 24 0 25 29 26 17 27 10 28 14 29 4 30 6 31 22 SEUSSF Moves and flips bits in a 'forward' pattern. SEUSSR Moves and flips bits in a 'reverse' pattern. TRUEINVERSE

SEUSSF bit permutation in text form:


TEST D,{#}S {WC/WZ/WCZ} - Test bit pattern

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0111110 CZI DDDDDDDDD SSSSSSSSS none parity of (D & S) ((D & S) == 0) 2 2 No

TEST performs a bitwise AND of the value in Source into that of Destination, but discards the result (Destination remains unchanged). Note that it is possible to encode TEST without any effects, which is entirely pointless.

If the WC or WCZ effect is specified, the C flag is set (1) if the result has odd parity (contains an odd number of high (1) bits), or is cleared (0) if it has even parity (contains an even number of high bits).

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination OR Source result equals zero, or is cleared (0) if it is non-zero.

Warning: Easy to confuse with TESTB

TESTN D,{#}S {WC/WZ/WCZ} - Test bit pattern (negative)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0111111 CZI DDDDDDDDD SSSSSSSSS none parity of (D & !S) ((D & !S) == 0) 2 2 No

TESTN performs a bitwise AND of the inverse of the value in Source into that of Destination, but discards the result (Destination remains unchanged). Note that it is possible to encode TESTN without any effects, which is entirely pointless.

If the WC or WCZ effect is specified, the C flag is set (1) if the result has odd parity (contains an odd number of high (1) bits), or is cleared (0) if it has even parity (contains an even number of high bits).

If the WZ or WCZ effect is specified, the Z flag is set (1) if the Destination OR Source result equals zero, or is cleared (0) if it is non-zero.

Warning: Easy to confuse with TESTBN

AND D,{#}S {WC/WZ/WCZ} - Bitwise AND

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0101000 CZI DDDDDDDDD SSSSSSSSS D parity of result Result == 0 2 2 No

AND performs a bitwise AND of the value in Source into that of Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result has odd parity (contains an odd number of high (1) bits), or is cleared (0) if it has even parity (contains an even number of high bits).

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result equals zero, or is cleared (0) if it is non-zero.

ANDN D,{#}S {WC/WZ/WCZ} - Bitwise AND (negative)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0101001 CZI DDDDDDDDD SSSSSSSSS D parity of result Result == 0 2 2 No

ANDN performs a bitwise AND of the inverse of the value in Source into that of Destination. That is, each high bit in Source will become low in Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result has odd parity (contains an odd number of high (1) bits), or is cleared (0) if it has even parity (contains an even number of high bits).

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result equals zero, or is cleared (0) if it is non-zero.

OR D,{#}S {WC/WZ/WCZ} - Bitwise OR

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0101010 CZI DDDDDDDDD SSSSSSSSS D parity of result Result == 0 2 2 No

OR performs a bitwise OR of the value in Source into that of Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result has odd parity (contains an odd number of high (1) bits), or is cleared (0) if it has even parity (contains an even number of high bits).

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result equals zero, or is cleared (0) if it is non-zero.

XOR D,{#}S {WC/WZ/WCZ} - Bitwise XOR

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0101011 CZI DDDDDDDDD SSSSSSSSS D parity of result Result == 0 2 2 No

XOR performs a bitwise XOR of the value in Source into that of Destination.

If the WC or WCZ effect is specified, the C flag is set (1) if the result has odd parity (contains an odd number of high (1) bits), or is cleared (0) if it has even parity (contains an even number of high bits).

If the WZ or WCZ effect is specified, the Z flag is set (1) if the result equals zero, or is cleared (0) if it is non-zero.


TESTB D,{#}S WC/WZ - Test bit

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100000 CZI DDDDDDDDD SSSSSSSSS none D[S[4:0]] D[S[4:0]] 2 2 No

TESTB D,{#}S ANDC/ANDZ - Test bit (AND with current flag)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100010 CZI DDDDDDDDD SSSSSSSSS none C/Z AND D[S[4:0]] C/Z AND D[S[4:0]] 2 2 No

TESTB D,{#}S ORC/ORZ - Test bit (OR with current flag)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100100 CZI DDDDDDDDD SSSSSSSSS none C/Z OR D[S[4:0]] C/Z OR D[S[4:0]] 2 2 No

TESTB D,{#}S XORC/XORZ - Test bit (XOR with current flag)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100110 CZI DDDDDDDDD SSSSSSSSS none C/Z XOR D[S[4:0]] C/Z XOR D[S[4:0]] 2 2 No

TESTB reads the state (0/1) of a bit in Destination designated by Source and either stores it as-is, or bitwise ANDs, ORs, or XORs it into the C or Z flag.

Source[4:0] indicates the bit number (0–31) to test.

If the WC or WZ effect is specified, the C or Z flag is overwritten with the state of the bit.

If the ANDC or ANDZ effect is specified, the C or Z flag is bitwise ANDed with the state of the bit.

If the ORC or ORZ effect is specified, the C or Z flag is bitwise ORed with the state of the bit.

If the XORC or XORZ effect is specified, the C or Z flag is bitwise XORed with the state of the bit.

See also TESTBN.

Warning: Easy to confuse with TEST.

TESTBN D,{#}S WC/WZ - Test bit (negative)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100001 CZI DDDDDDDDD SSSSSSSSS none !D[S[4:0]] !D[S[4:0]] 2 2 No

TESTBN D,{#}S ANDC/ANDZ - Test bit (negative, AND with current flag)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100011 CZI DDDDDDDDD SSSSSSSSS none C/Z AND !D[S[4:0]] C/Z AND !D[S[4:0]] 2 2 No

TESTBN D,{#}S ORC/ORZ - Test bit (negative, OR with current flag)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100101 CZI DDDDDDDDD SSSSSSSSS none C/Z OR !D[S[4:0]] C/Z OR !D[S[4:0]] 2 2 No

TESTBN D,{#}S XORC/XORZ - Test bit (negative, XOR with current flag)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100111 CZI DDDDDDDDD SSSSSSSSS none C/Z XOR !D[S[4:0]] C/Z XOR !D[S[4:0]] 2 2 No

TESTBN reads the state (0/1) of a bit in Destination designated by Source, inverts the result, and either stores it (the inverse value) as-is, or bitwise ANDs, ORs, or XORs it into the C or Z flag.

Source[4:0] indicates the bit number (0–31) to test and invert.

If the WC or WZ effect is specified, the C or Z flag is overwritten with the inverse state of the bit.

If the ANDC or ANDZ effect is specified, the C or Z flag is bitwise ANDed with the inverse state of the bit.

If the ORC or ORZ effect is specified, the C or Z flag is bitwise ORed with the inverse state of the bit.

If the XORC or XORZ effect is specified, the C or Z flag is bitwise XORed with the inverse state of the bit.

See also TESTB.

Warning: Easy to confuse with TESTN.

{ SETQ {#}Q }
BITL D,{#}S {WCZ} - Clear bit(s)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100000 CZI DDDDDDDDD SSSSSSSSS D original D[S[4:0]] original D[S[4:0]] 2 2 No

{ SETQ {#}Q }
BITH D,{#}S {WCZ} - Set bit(s)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100001 CZI DDDDDDDDD SSSSSSSSS D original D[S[4:0]] original D[S[4:0]] 2 2 No

{ SETQ {#}Q }
BITNOT D,{#}S {WCZ} - Toggle bit(s)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100111 CZI DDDDDDDDD SSSSSSSSS D original D[S[4:0]] original D[S[4:0]] 2 2 No

{ SETQ {#}Q }
BITRND D,{#}S {WCZ} - Randomize bit(s)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100110 CZI DDDDDDDDD SSSSSSSSS D original D[S[4:0]] original D[S[4:0]] 2 2 No

{ SETQ {#}Q }
BITC D,{#}S {WCZ} - Set bit(s) to C

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100010 CZI DDDDDDDDD SSSSSSSSS D original D[S[4:0]] original D[S[4:0]] 2 2 No

{ SETQ {#}Q }
BITNC D,{#}S {WCZ} - Set bit(s) to !C

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100011 CZI DDDDDDDDD SSSSSSSSS D original D[S[4:0]] original D[S[4:0]] 2 2 No

{ SETQ {#}Q }
BITZ D,{#}S {WCZ} - Set bit(s) to Z

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100100 CZI DDDDDDDDD SSSSSSSSS D original D[S[4:0]] original D[S[4:0]] 2 2 No

{ SETQ {#}Q }
BITNZ D,{#}S {WCZ} - Set bit(s) to !Z

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0100101 CZI DDDDDDDDD SSSSSSSSS D original D[S[4:0]] original D[S[4:0]] 2 2 No

MUXC D,{#}S {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0101100 CZI DDDDDDDDD SSSSSSSSS D parity of result Result == 0 2 2 No

MUXNC D,{#}S {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0101101 CZI DDDDDDDDD SSSSSSSSS D parity of result Result == 0 2 2 No

MUXZ D,{#}S {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0101110 CZI DDDDDDDDD SSSSSSSSS D parity of result Result == 0 2 2 No

MUXNZ D,{#}S {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 0101111 CZI DDDDDDDDD SSSSSSSSS D parity of result Result == 0 2 2 No

{ SETQ {#}Q }
MUXQ D,{#}S

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001111 10I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

MUXQ copies all bits from Source corresponding to high (1) bits of the Q Register into the corresponding bits of Destination. All other Destination bits are left as-is.

The current Q value is always used, regardless of whether MUXQ is directly preceded by SETQ (i.e. whether the "SETQ Flag" is set) or not.

MUXNIBS D,{#}S - Copy non-zero nibbles

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001111 01I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

MUXNIBS copies any non-zero nibbles from Source into the corresponding nibbles of Destination and leaves the rest of Destination's nibbles as-is.

TODO more detail

MUXNITS D,{#}S - Copy non-zero bit pairs

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001111 00I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

MUXNITS copies any non-zero bit pairs from Source into the corresponding bit pairs of Destination and leaves the rest of Destination's bit pairs as-is.

TODO more detail

Flag manipulation

MODCZ c,z {WC/WZ/WCZ} - Modify Flags

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ1 0cccczzzz 001101111 none Per cccc Per zzzz 2 2 No

MODC, MODZ, or MODCZ sets or clears the C and/or Z flag based on the mode described by the given modifier symbols and the current state of the C and Z flags. The WC, WZ, and WCZ effects are required to affect the designated flag. Note that it is possible to encode MODCZ without any effects, which is entirely pointless.

These flag modifier instructions allow code to preset flags to a desired state which may be required for entry into certain code routines, or to set a special state based on multiple events that are otherwise not possible to realize with a single instruction.

The possible modifiers are:

Encoding Primary Name Alternate 1 Alternate 2 Description
%0000 _CLR     Always clear flag
%0001 _NC_AND_NZ _NZ_AND_NC _GT Set flag if C=0 AND Z=0
%0010 _NC_AND_Z _Z_AND_NC   Set flag if C=0 AND Z=1
%0011 _NC   _GE Set flag if C=0
%0100 _C_AND_NZ _NZ_AND_C   Set flag if C=1 AND Z=0
%0101 _NZ   _NE Set flag if Z=0
%0110 _C_NE_Z _Z_NE_C   Set flag if C!=Z
%0111 _NC_OR_NZ _NZ_OR_NC   Set flag if C=0 OR Z=0
%1000 _C_AND_Z _Z_AND_C   Set flag if C=1 AND Z=1
%1001 _C_EQ_Z _Z_EQ_C   Set flag if C=Z
%1010 _Z   _E Set flag if Z=1
%1011 _NC_OR_Z _Z_OR_NC   Set flag if C=0 OR Z=1
%1100 _C   _LT Set flag if C=1
%1101 _C_OR_NZ _NZ_OR_C   Set flag if C=1 OR Z=0
%1110 _C_OR_Z _Z_OR_C   Set flag if C=1 OR Z=1
%1111 _SET     Always set flag

Note the logical nature of the encoding: Each bit in the modifier corrosponds to one possible state of [C,Z].

Thus, every modifier with one bit set is an "x AND y" type (only one of four possible states sets the flag), every modifier with 3 bits set is an "x OR y" type (all but one state sets the flag).

MODC c {WC} - Modify C Flag

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 C01 0cccc0000 001101111 none Per cccc --- 2 2 No

MODC is an alias for MODCZ without the Z parameter.

MODZ z {WZ} - Modify Z Flag

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 0Z1 00000zzzz 001101111 none --- Per zzzz 2 2 No

MODZ is an alias for MODCZ without the C parameter.

WRC D - Get C into register

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001101100 D --- --- 2 2 No

WRC writes the state of C (0 or 1) to Destination. The entire register is overwritten.

WRNC D - Get !C into register

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001101101 D --- --- 2 2 No

WRNC writes the inverse state of C (0 or 1) to Destination. The entire register is overwritten.

WRZ D - Get Z into register

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001101110 D --- --- 2 2 No

WRZ writes the state of Z (0 or 1) to Destination. The entire register is overwritten.

WRNZ D - Get !Z into register

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001101111 D --- --- 2 2 No

WRNZ writes the inverse state of Z (0 or 1) to Destination. The entire register is overwritten.

Other

CRCBIT D,{#}S - Advance CRC (one bit)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001110 10I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

CRCBIT feeds one bit, taken from the C flag, into the CRC checksum in Destination, using the polynomial given in Source.

CRCBIT D,S is equivalent to the following sequence (except that CRCBIT does not change the C flag):

        TESTB  D,#0 xorc
        SHR    D,#1
   if_c XOR    D,S

{ SETQ {#}Q }
CRCNIB D,{#}S - Advance CRC (four bits)

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1001110 11I DDDDDDDDD SSSSSSSSS D --- --- 2 2 Yes

CRCNIB feeds one nibble, taken from the top 4 bits of the Q Register, into the CRC checksum in Destination, using the polynomial given in Source. The top bit of Q is processed first. Afterwards, Q is shifted left by 4 bits.

To process an entire long, the following sequence can be used:

        SETQ  value
        REP   #1,#8
        CRCNIB checksum,polynomial

XORO32 D - Generate pseudo-random number

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 000 DDDDDDDDD 001101000 D --- --- 2 2 Yes

XORO32 generates a pseudo-random number based on the seed value in Destination. The next seed value is written back into Destination and the generated pseudo-random number is substituted as the next instruction's Source value (and as a side effect, also written to the Q Register).

Destination's value should never be zero, since that causes the seed to stay zero.

The algorithm used is xoroshiro32++, stepped twice to generate 2x16 bits of data. Due to this, some 32-bit numbers are never generated. Ideal properties are only guaranteed if only the top or bottom 16 bits of the generated number are used. Any subset of bits from either the upper or lower half are also equidistributed.

A software implementation of the algorithm in Spin2:

CON
    A = 13, B = 5, C = 10, D = 9
PUB xoro32_soft(seed) : state,val
  state, val.word[0] := xoro32_half(seed)
  state, val.word[1] := xoro32_half(state)

PRI xoro32_half(seed) : state,val
  val.word[0] := rol16(seed.word[0]+seed.word[1],D)+seed.word[0]
  state := seed
  state.word[1] ^= state.word[0]
  state.word[0] := rol16(state.word[0],A) ^ (state.word[1]<<B) ^ state.word[1]
  state.word[1] := rol16(state.word[1],C)

PRI rol16(val,amount) :r
  val.word[1] := val.word[0]
  return (val rol amount) zerox 15