Interrupts
Brain hurt.
The Propeller 2 features a 3-level interrupt system (int1 through int3), plus a "hidden" debugger interrupt (int0). Lower level interrupts take priority over higher-level interrupts.
TODO further explain interrupt vectors/returns
Setup Instructions
SETINT1 {#}D - Configure Interrupt 1
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 00L DDDDDDDDD 000100101 | none | --- | --- | 2 | 2 | No |
|---|
SETINT2 {#}D - Configure Interrupt 2
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 00L DDDDDDDDD 000100110 | none | --- | --- | 2 | 2 | No |
|---|
SETINT3 {#}D - Configure Interrupt 3
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 00L DDDDDDDDD 000100111 | none | --- | --- | 2 | 2 | No |
|---|
SETINTx configures which Event ID triggers the respective interrupt based on Destination. An event ID of zero (or INT_OFF) disables the interrupt (EVENT_INT is not available).
Control Instructions
ALLOWI - Enable interrupts
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 000 000100000 000100100 | none | --- | --- | 2 | 2 | No |
|---|
STALLI - Disable interrupts
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 000 000100001 000100100 | none | --- | --- | 2 | 2 | No |
|---|
TRGINT1 - Force Interrupt 1
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 000 000100010 000100100 | none | --- | --- | 2 | 2 | No |
|---|
TRGINT2 - Force Interrupt 2
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 000 000100011 000100100 | none | --- | --- | 2 | 2 | No |
|---|
TRGINT3 - Force Interrupt 3
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 000 000100100 000100100 | none | --- | --- | 2 | 2 | No |
|---|
NIXINT1 - Cancel Interrupt 1
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 000 000100101 000100100 | none | --- | --- | 2 | 2 | No |
|---|
NIXINT2 - Cancel Interrupt 2
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 000 000100110 000100100 | none | --- | --- | 2 | 2 | No |
|---|
NIXINT3 - Cancel Interrupt 3
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 000 000100111 000100100 | none | --- | --- | 2 | 2 | No |
|---|
Interrupt Returns
RETI0 - Return from Debug Interrupt
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1011001 110 111111111 111111111 | D | --- | --- | 4 | 13..20 | No |
|---|
RETI1 - Return from Interrupt 1
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1011001 110 111111111 111110101 | D | --- | --- | 4 | 13..20 | No |
|---|
RETI2 - Return from Interrupt 2
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1011001 110 111111111 111110011 | D | --- | --- | 4 | 13..20 | No |
|---|
RETI3 - Return from Interrupt 3
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1011001 110 111111111 111110001 | D | --- | --- | 4 | 13..20 | No |
|---|
TODO
RETI0, RETI1, RETI2 and RETI3 are used to return from the respective interrupt. The next time the intterupt is triggered, it will start again from the current value of IJMPx.
Technically aliases for CALLD INB,IRETx WCZ. Use of the CALLD opcode with IRETx registers has the side-effect of clearing the interrupt state.
RESI0 - Resume from Debug Interrupt
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1011001 110 111111110 111111111 | D | --- | --- | 4 | 13..20 | No |
|---|
RESI1 - Resume from Interrupt 1
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1011001 110 111110100 111110101 | D | --- | --- | 4 | 13..20 | No |
|---|
RESI2 - Resume from Interrupt 2
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1011001 110 111110010 111110011 | D | --- | --- | 4 | 13..20 | No |
|---|
RESI3 - Resume from Interrupt 3
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1011001 110 111110000 111110001 | D | --- | --- | 4 | 13..20 | No |
|---|
TODO
RESI0, RESI1, RESI2 and RETS3 are used to "resume" from the respective interrupt. The next time the intterupt is triggered, it will continue execution at the instruction after the RESIx instruction.
Technically aliases for CALLD IJMPx,IRETx WCZ. Use of the CALLD opcode with IRETx registers has the side-effect of clearing the interrupt state.
Debug-Related
BRK {#}D
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 00L DDDDDDDDD 000110110 | none | --- | --- | 2 | 2 | No |
|---|
BRK is used to programmatically trigger a debug interrupt. The value of D is latched and can be used by the debugger code.
NOTE: This instruction can not be used with a condition code. See the relvant errata entry.