Events

Brain hurt.

Event ID Set when Cleared by
(in addition to POLL/WAIT/J/JN)
EVENT_INT 0 Interrupt occurs (except debug)  
EVENT_CT1 1 CT1 target reached ADDCT1
EVENT_CT2 2 CT2 target reached ADDCT2
EVENT_CT3 3 CT3 target reached ADDCT3
EVENT_SE1 4 SE1 selected event occurs SETSE1
EVENT_SE2 5 SE2 selected event occurs SETSE2
EVENT_SE3 6 SE3 selected event occurs SETSE3
EVENT_SE4 7 SE4 selected event occurs SETSE4
EVENT_PAT 8 Pattern match/mismatch occurs SETPAT
EVENT_FBW 9 FIFO Block wrapped WRFAST,RDFAST,FBLOCK
EVENT_XMT 10 Streamer ready for command XINIT,XZERO,XCONT
EVENT_XFI 11 Streamer runs out of commands XINIT,XZERO,XCONT
EVENT_XRO 12 Streamer NCO rolls over XINIT,XZERO,XCONT
EVENT_XRL 13 Streamer reads LUT address $1FF  
EVENT_ATN 14 COGATN attention strobe occurs  
EVENT_QMT 15 GETQX/GETQY executes without any CORDIC results available or in progress.  

Selectable Events

Each cog can track up to four selectable Pin, LUT, or Lock(TODO link?) events, SE1 through SE4. The event to be monitored is selected by using the SETSEx instruction(s).

Setup Instructions

SETSE1 {#}D

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 00L DDDDDDDDD 000100000 none --- --- 2 2 No

SETSE2 {#}D

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 00L DDDDDDDDD 000100001 none --- --- 2 2 No

SETSE3 {#}D

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 00L DDDDDDDDD 000100010 none --- --- 2 2 No

SETSE4 {#}D

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 00L DDDDDDDDD 000100011 none --- --- 2 2 No

SETSEx selects the event to be monitored by the corrosponding SEx event flag according to Destination. TODO words

Pin Events

LUT Events

You can select $1FC..$1FF for the LUT read or write address event sensitivity with bits AA. (TODO less confusing wording)

Lock Events

ADDCT1 D,{#}S

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1010011 00I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

ADDCT2 D,{#}S

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1010011 01I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

ADDCT3 D,{#}S

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1010011 10I DDDDDDDDD SSSSSSSSS D --- --- 2 2 No

ADDCT1, ADDCT2, or ADDCT3 set the hidden CT1, CT2, or CT3 event trigger register (respectively) to the value of Destination + Source. The result is also written to Destination.

The respective CTx event flag is set when the trigger register matches the bottom 32 bits of the global CT counter. ADDCTx clears this flag again.

TODO: More detail

SETPAT {#}D,{#}S

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1011111 1LI DDDDDDDDD SSSSSSSSS none --- --- 2 2 No

Set pin pattern for 'Pattern match/mismatch' event. C flag selects INA/INB, Z flag selects match/mismatch, Destination provides mask value, Source provides match value.

TODO: More detail

Attention

COGATN {#}D

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 00L DDDDDDDDD 000111111 none --- --- 2 2 No

COGATN strobes the attention signal for one or more cogs. Destination bit positions 7:0 represent cogs 7 through 0; high (1) bits indicate the cog(s) to signal. The receiving cog(s) will have their ATN event flag set, and can use any of the attention monitor instructions (JATN, JNATN, POLLATN, WAITATN) or interrupts to respond and clear the flag.

        COGATN #%00100010

In the intended use case, the cog receiving an attention request knows which other cog is strobing it and how to respond. In cases where multiple cogs may request the attention of a single cog, some messaging structure may need to be implemented in Hub RAM to differentiate requests. (TODO: Perhaps mention lock SEs?)

Poll Instructions

POLLINT {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000000000 000100100 none INT event occured INT event occurred 2 2 No

POLLCT1 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000000001 000100100 none CT1 event occured CT1 event occurred 2 2 No

POLLCT2 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000000010 000100100 none CT2 event occured CT2 event occurred 2 2 No

POLLCT3 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000000011 000100100 none CT3 event occured CT3 event occurred 2 2 No

POLLSE1 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000000100 000100100 none SE1 event occured SE1 event occurred 2 2 No

POLLSE2 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000000101 000100100 none SE2 event occured SE2 event occurred 2 2 No

POLLSE3 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000000110 000100100 none SE3 event occured SE3 event occurred 2 2 No

POLLSE4 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000000111 000100100 none SE4 event occured SE4 event occurred 2 2 No

POLLPAT {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000001000 000100100 none PAT event occured PAT event occurred 2 2 No

POLLFBW {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000001001 000100100 none FBW event occured FBW event occurred 2 2 No

POLLXMT {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000001010 000100100 none XMT event occured XMT event occurred 2 2 No

POLLXFI {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000001011 000100100 none XFI event occured XFI event occurred 2 2 No

POLLXRO {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000001100 000100100 none XRO event occured XRO event occurred 2 2 No

POLLXRL {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000001101 000100100 none XRL event occured XRL event occurred 2 2 No

POLLATN {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000001110 000100100 none ATN event occured ATN event occurred 2 2 No

POLLQMT {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000001111 000100100 none QMT event occured QMT event occurred 2 2 No

Wait Instructions

{ SETQ {#}Q }
WAITINT {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000010000 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITCT1 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000010001 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITCT2 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000010010 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITCT3 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000010011 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITSE1 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000010100 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITSE2 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000010101 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITSE3 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000010110 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITSE4 {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000010111 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITPAT {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000011000 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITFBW {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000011001 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITXMT {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000011010 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITXFI {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000011011 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITXRO {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000011100 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITXRL {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000011101 000100100 none timeout timeout 2+ 2+ No

{ SETQ {#}Q }
WAITATN {WC/WZ/WCZ}

Encoding Register
Written
C Flag Z Flag Cycles
(cogexec)
Cycles
(hubexec)
IRQ
Shield
EEEE 1101011 CZ0 000011110 000100100 none timeout timeout 2+ 2+ No