Hub FIFO
Each Cog possesses a FIFO (First-In-First-Out) queue that can be used to read or write sequential data from/to Hub RAM.
It can either be used to feed the Streamer, to execute code from Hub RAM (HubExec) or manually using the RFxxxx and WRxxxx instructions.
Control Instructions
RDFAST {#}D,{#}S - Start FIFO read
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1100011 1LI DDDDDDDDD SSSSSSSSS | none | --- | --- | 2 or WRFAST finish + 10..17 | FIFO IN USE | No |
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RDFAST prepares the FIFO queue to read from the address given in Source. Additionally, if Destination[13:0] is non-zero, it is used as a count of 64-byte blocks after which the FIFO read address wraps back around. If this is used, the address in Source must be long-aligned.
Normally, RDFAST will block while the FIFO completes any pending writes and fills up with read data, but if Destination[31] is set, it doesn't. Attempting to use the FIFO while it is not yet ready will cause zeroes to be read. In the usual case (no pending WRFAST data), the FIFO is guaranteed to be ready after 13 cycles.
SILICON ERRATA: When using RDFAST with Destination[31] set, using other, (non-FIFO) Hub RAM read/write instructions while the FIFO is not yet ready can cause issues.
TODO reword more detail
WRFAST {#}D,{#}S - Start FIFO write
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1100100 0LI DDDDDDDDD SSSSSSSSS | none | --- | --- | 2 or WRFAST finish + 3 | FIFO IN USE | No |
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WRFAST prepares the FIFO queue to write to the address given in Source. Additionally, if Destination[13:0] is non-zero, it is used as a count of 64-byte blocks after which the FIFO read address wraps back around. If this is used, the address in Source must be long-aligned.
Normally, WRFAST will block while the FIFO completes any pending writes, but if Destination[31] is set, it doesn't. Attempting to use the FIFO while it is not yet ready may result in garbled data.
TODO reword more detail
FBLOCK {#}D,{#}S
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1100100 1LI DDDDDDDDD SSSSSSSSS | none | --- | --- | 2 | FIFO IN USE | No |
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FBLOCK sets the next wrap address and length for the FIFO queue.
TODO
GETPTR D - Get current FIFO position
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 000 DDDDDDDDD 000110100 | D | --- | --- | 2 | FIFO IN USE | No |
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GETPTR gets the current FIFO address (from/to which the next data will be read/written) into Destination.
TODO: I think this only works right with RFxxxx/WFxxxx and XBYTE? (i.e. not with streamer or hubexec)
Read Instructions
RFLONG D {WC/WZ/WCZ} - Read long from FIFO
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 CZ0 DDDDDDDDD 000010010 | D | MSB of long | Result == 0 | 2 | FIFO IN USE | No |
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RFWORD D {WC/WZ/WCZ} - Read word from FIFO
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 CZ0 DDDDDDDDD 000010001 | D | MSB of word | Result == 0 | 2 | FIFO IN USE | No |
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RFBYTE D {WC/WZ/WCZ} - Read byte from FIFO
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 CZ0 DDDDDDDDD 000010000 | D | MSB of byte | Result == 0 | 2 | FIFO IN USE | No |
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RFVAR D {WC/WZ/WCZ} - Read variable-length value from FIFO (unsigned)
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 CZ0 DDDDDDDDD 000010011 | D | 0 | Result == 0 | 2 | FIFO IN USE | No |
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RFVARS D {WC/WZ/WCZ} - Read variable-length value from FIFO (signed)
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 CZ0 DDDDDDDDD 000010100 | D | MSB of value | Result == 0 | 2 | FIFO IN USE | No |
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Write Instructions
WFLONG {#}D - Write long to FIFO
| Encoding | Register Written | C Flag | Z Flag | Cycles (cogexec) | Cycles (hubexec) | IRQ Shield | EEEE 1101011 00L DDDDDDDDD 000010111 | none | --- | --- | 2 | FIFO IN USE | No |
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